Patent · US Active

Fusion to enhance early address generation of load instructions in a microprocessor

US11163571B1 · kind B1 · utility

2Cited by

7References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Brian D. Barrick · Pflugerville, US
Sundeep Chadha · Austin, US
Sheldon B. Levenstein · Austin, US
Phillip G. Williams · Vestal, US
Niels Fricke · Herrenberg, DE
Dung Q. Nguyen · Austin, US
Brian W. Thompto · Austin, US
Christian Zoellin · Waiblingen, DE

Key dates

Filing date	Jul 29, 2020
Grant date	Nov 2, 2021
Priority date	—
Expiry date	Jul 29, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/30167
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.