Heterogeneous execution pipeline across different processor architectures and FPGA fabric
US11163605B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jan 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.