Two-layer code with low parity cost for memory sub-systems
US11164652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | May 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.