Spacer-defined process for lithography-etch double patterning for interconnects
US11164772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Feb 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.