Patent · US Active

Packaged integrated circuit having stacked die and method for making

US11164826B2 · kind B2 · utility

0Cited by

3References

14Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Burton J. Carpenter · Austin, US
Fred T. Brauchler · Canton, US

Key dates

Filing date	Aug 30, 2019
Grant date	Nov 2, 2021
Priority date	—
Expiry date	Nov 22, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A packaged integrated circuit (IC) device includes a first IC die, a first layer of adhesive on a first major surface of the first IC die, and an isolation layer over the first layer of adhesive. The isolation layer has a first major surface and a second major surface, and the second major surface of the isolation layer is between the first layer of adhesive and the first major surface. The packaged IC device also includes a first inductor coil on the first major surface of the isolation layer, a second layer of adhesive on the isolation layer, and a second IC die on the second layer of adhesive.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.