Glitch-free digital controlled delay line apparatus and method
US11165432B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Nov 6, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes a delay line including at least a first group of delay elements. The delay line is responsive to a first digital delay code to delay an input signal by a first delay value, and responsive to a change from the first digital delay code to a second digital delay code to delay the input signal by a second delay value. Control circuitry generates the first and second digital delay codes. Glitch monitoring circuitry couples to the control circuitry to conditionally gate the change from the first digital delay code to the second digital delay code based on a prediction of a glitch condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.