Method for co-packaging light engine chiplets on switch substrate
US11165509B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jun 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J14/0278
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for co-packaging multiple light engines in a switch module is provided. The method includes providing a module substrate with a minimum lateral dimension no greater than 110 mm. The module substrate is configured with a first mounting site at a center region and a plurality of second mounting sites distributed densely along the peripheral sides. The method includes disposing a main die with a switch processor chip at the first mounting site. The switch processor chip is configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. The method further includes mounting a plurality of chiplet dies respectively into the plurality of second mounting sites. Each chiplet die is configured to be a packaged light engine with a minimum lateral dimension to allow a maximum number of chiplet dies with <50 mm from the main die for extra-short-reach data interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.