Multiple modes for handling overflow conditions resulting from arithmetic operations
US11169777B2 · kind B2 · utility
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23Claims
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Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for handling overflow conditions resulting from arithmetic operations involving floating point numbers. An indication is stored as part of a thread's context indicating one of two possible modes for handling overflow conditions. In a first mode, a result of an arithmetic operation is set to the limit representable in the floating point format. In a second mode, a result of an arithmetic operation is set to a NaN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.