Mrudula Gore
14Patents
2h-index
9Co-inventors
39Inventor score
Filing activity: Feb 15, 2019 → Apr 5, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11644884B2 | Controlling a processor clock | Emerging Cross-Sectional Technologies | 2 | Active |
| US11119559B2 | Controlling a processor clock | Emerging Cross-Sectional Technologies | 2 | Active |
| US11966740B2 | Use of multiple different variants of floating point number formats in floating point operations on a per-operand basis | Physics | 1 | Active |
| US11467833B2 | Load-store instruction for performing multiple loads, a store, and strided increment of multiple addresses | Physics | 1 | Active |
| US11567768B2 | Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times | Emerging Cross-Sectional Technologies | 0 | Active |
| US11169778B2 | Converting floating point numbers to reduce the precision | Physics | 0 | Active |
| US12399717B2 | Processing device for intermediate value scaling | Physics | 0 | Active |
| US11169777B2 | Multiple modes for handling overflow conditions resulting from arithmetic operations | Physics | 0 | Active |
| US11449309B2 | Hardware module for converting numbers | Physics | 0 | Active |
| US12430130B2 | Floating point norm instruction | Physics | 0 | Active |
| US12367043B2 | Multi-threaded barrel processor using shared weight registers in a common weights register file | Physics | 0 | Active |
| US11023239B2 | Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions | General | 0 | Revoked |
| US12001263B2 | Controlling a processor clock | Emerging Cross-Sectional Technologies | 0 | Active |
| US11061679B2 | Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.