Memory cells and methods of forming a capacitor including current leakage paths having different total resistances

US11170834B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Michael Mutch · Chardon, US
• Ashonita A. Chavan · Boise, US
• Sameer Chhajed · Boise, US
• Beth R. Cook · Meridian, US
• Kamal Kumar Muthukrishnan · Boise, US
• Durai Vishak Nirmal Ramaswamy · Boise, US
• Lance Williamson · Boise, US

Key dates

• Filing date: Jul 10, 2019
• Grant date: Nov 9, 2021
• Expiry date: Oct 13, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/682
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.