Identifying high impedance faults in a memory device
US11170837B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.