Memory devices and methods of forming memory devices
US11171146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | May 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.