Method for forming a MFMIS memory device

US11171157B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Sheng-Chih Lai · Dashulong, TW
• Chung-Te Lin · Tainan, TW

Key dates

• Filing date: May 5, 2020
• Grant date: Nov 9, 2021
• Expiry date: May 5, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/033

Abstract

Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.