Techniques for reliable clock speed change and associated circuits and methods
US11171659B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2021 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for reliable clock speed change and associated circuits and methods are disclosed. Internal voltage supplies of semiconductor devices may include oscillators and charge pump circuits. The oscillator may include at least two clock paths for generating clock signals having different clock frequencies, which can be provided to the charge pump circuit. Further, the oscillator may generate a reset signal configured to activate one clock path over the other (e.g., changing clock speeds). In some embodiments, the oscillator includes a flip-flop to align the reset signal with respect to an edge of an input clock signal supplied to the oscillator such that unintentional (undesired, unexpected) features in the output signal of the oscillator can be avoided when the oscillator changes clock speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.