Parity generation circuits for a plurality of error correction levels, memory controllers, and memory modules including the parity generation circuits
US11171670B2 · kind B2 · utility
1Cited by
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14Claims
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Key dates
| Filing date | Jun 24, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jun 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.