Erasure coding techniques for flash memory
US11175984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2019 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Apr 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are use, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.