Built-in self-testing and failure correction circuitry
US11177015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jun 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.