Method for packaging a chip
US11177141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jul 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H9/0542
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for packaging a chip and a chip package structure are provided. The method is used to package the chip including an acoustic filter. The packaging substrate and the device wafer are welded together, wherein the edge of the device wafer is chamfered, the packaging substrate is provided with a groove, the chamfered portion of device wafer is aligned with the groove on the substrate, and then a mask is disposed. The surface of the mask facing the device wafer is an inclined surface, forming a wedge-shaped opening. A package resin material is printed, wherein the package resin material falls into the groove through the inclined surface of the mask, and a package resin film is formed between the groove and the chamfer. The mask is removed along the first surface toward the second surface. The package resin is cured in a position where the resin film is located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.