Reducing glitch power in digital circuits
US11177805B1 · kind B1 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jun 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.