Dedicated communications cache
US11182103B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jan 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.