Technologies for preserving error correction capability in compute-in-memory operations
US11182242B2 · kind B2 · utility
6Cited by
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21Claims
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Key dates
| Filing date | Jun 21, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.