System, apparatus and method for memory mirroring in a buffered memory architecture
US11182313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.