Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same
US11182529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h≥1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.