Memory device
US11183246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Sep 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first plane defined in a second wafer stacked on a first wafer; a second plane defined in a third wafer stacked on the second wafer, and overlapping with the first plane in a vertical direction; a first page buffer circuit including a first column driver coupled to bit lines of the first plane and a first column operator; and a second page buffer circuit including a second column driver coupled to bit lines of the second plane and a second column operator. The first column driver is disposed in the second wafer, the second column driver is disposed in the third wafer and overlaps with the first column driver in the vertical direction, and the first and second column operators are disposed in a cell region of the first wafer and overlap with the first and second planes in the vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.