Memory cell having top and bottom electrodes defining recesses
US11183503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.