Process for fabricating medium-voltage transistors and corresponding integrated circuit
US11183505B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jul 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.