Super-HPC error correction code
US11184026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/618
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.