Multi-level system memory with near memory capable of storing compressed cache lines
US11188467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Mar 24, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.