Pin accessibility prediction engine
US11188705B2 · kind B2 · utility
0Cited by
9References
21Claims
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Key dates
| Filing date | May 15, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.