Non-destructive mode cache programming in NAND flash memory devices
US11189326B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.