Memory cell arrangement and methods thereof

US11189331B1 · kind B1 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventors

• Antoine Benoist · Dresden, DE
• Marko Noack · Dresden, DE

Key dates

• Filing date: Jul 15, 2020
• Grant date: Nov 30, 2021
• Expiry date: Jul 15, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/701
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.