Subtractive RIE interconnect
US11189528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Apr 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for constructing interconnects by employing a subtractive etch process. The method includes forming a plurality of first conductive lines within an interlayer dielectric, depositing dielectric layers over the plurality of first conductive lines, depositing a photoresist layer over the dielectric layers, patterning the photoresist layer to create vias to top surfaces of one or more of the plurality of first conductive lines, and depositing a conductive material such that the conductive material fills the vias and provides for a sheet of metal for second conductive lines formed above the first conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.