Inventor · Watervliet, NY, US

Balasubramanian S. Pranatharthi Haran

23Patents
6h-index
43Co-inventors
65Inventor score

Filing activity: Sep 7, 2004 → Aug 14, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US8772168B2 Formation of the dielectric cap layer for a replacement gate structure Electricity 25 Active
US9741609B1 Middle of line cobalt interconnection Electricity 15 Active
US8101518B2 Method and process for forming a self-aligned silicide contact Electricity 10 Active
US7544610B2 Method and process for forming a self-aligned silicide contact Electricity 9 Expired
US8957465B2 Formation of the dielectric cap layer for a replacement gate structure Electricity 7 Active
US9455254B2 Methods of forming a combined gate and source/drain contact structure and the resulting device Electricity 7 Active
US10497612B2 Methods of forming contact structures on integrated circuit products Electricity 4 Active
US7501345B1 Selective silicide formation by electrodeposit displacement reaction Electricity 4 Active
US7914970B2 Mixed lithography with dual resist and a single pattern transfer Emerging Cross-Sectional Technologies 4 Active
US8698318B2 Superfilled metal contact vias for semiconductor devices Electricity 4 Active
US10600638B2 Nanosheet transistors with sharp junctions Electricity 3 Active
US11133217B1 Late gate cut with optimized contact trench size Electricity 2 Active
US11164782B2 Self-aligned gate contact compatible cross couple contact formation Electricity 2 Active
US8334090B2 Mixed lithography with dual resist and a single pattern transfer Emerging Cross-Sectional Technologies 2 Active
US9704991B1 Gate height and spacer uniformity Electricity 1 Active
US11171054B2 Selective deposition with SAM for fully aligned via Electricity 0 Active
US11355633B2 Vertical field effect transistor with bottom source-drain region Electricity 0 Active
US11302637B2 Interconnects including dual-metal vias Electricity 0 Active
US11430651B2 Nanosheet transistors with sharp junctions Electricity 0 Active
US11152464B1 Self-aligned isolation for nanosheet transistor Electricity 0 Active
US11189528B2 Subtractive RIE interconnect Electricity 0 Active
US10872809B2 Contact structures for integrated circuit products Electricity 0 Active
US10586741B2 Gate height and spacer uniformity Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.