Method and apparatus for on-chip stress detection
US11189536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.