Semiconductor structure with polyimide packaging and manufacturing method
US11189538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | May 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1205
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.