Placing top vias at line ends by selective growth of via mask from line cut dielectric
US11189561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Mar 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.