Maintaining height of alignment key in semiconductor devices
US11189572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Jun 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.