Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
US11189600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.