Insulated gate power semiconductor device and method for manufacturing such device
US11189688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Sep 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.