Method for forming a superjunction transistor device
US11189690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Dec 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.