Embedded MRAM device formation with self-aligned dielectric cap
US11189783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Oct 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/841
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.