Latch circuit, memory device and method
US11190169B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.