Latch-based level shifter circuit with self-biasing
US11190172B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Sep 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.