Compressed test patterns for a field programmable gate array

US11193975B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Christopher J. Nelson · Hiram, US
• Shelby G. ROLLINS · Hillsboro, US
• Hiren V. Tilala · Chandler, US
• Matthew Hendricks · Redwood City, US
• Sundar V. PATHY · Chandler, US
• Timothy J. Callahan · Hillsboro, US
• Jared Pager · Portland, US
• James Neeb · Gilbert, US
• Bradly L. Inman · Hillsboro, US
• Stephen S. Sturges · Portland, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Dec 7, 2021
• Expiry date: Mar 18, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318547
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.