Semiconductor memory device, and memory system having the same
US11194653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.