Patent · US Active

Memory cell arrangement and methods thereof

US11195589B1 · kind B1 · utility

10Cited by

3References

20Claims

0Family size

Assignee

Ferroelectric Memory GmbH · DE

Inventors

Johannes Ocker · Dresden, DE
Haidi Zhou · Dresden, DE
Stefan Müller · Wetzlar, DE

Key dates

Filing date	Jul 15, 2020
Grant date	Dec 7, 2021
Priority date	—
Expiry date	Jul 15, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/32
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

According to various aspects, a memory cell arrangement is provided, the memory cell arrangement including a control circuit configured to carry out a de-trapping writing scheme to write at least one memory cell of the memory cell arrangement into a memory state, the de-trapping writing scheme including providing one or more write voltage pulses and one or more de-trapping voltage pulses at the at least one memory cell, wherein the one or more de-trapping voltage pulses have opposite polarity with respect to the one or more write voltage pulses, and wherein one or more properties of the one or more write voltage pulses and of the one or more de-trapping voltage pulses are varied as long as the memory cell is not in the memory state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.