Epitaxial growth constrained by a template
US11195715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02521
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.