Integration of a III-V device on a Si substrate
US11195767B2 · kind B2 · utility
1Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Jan 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/82
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.