Inventor · Linden, BE

Liesbeth Witters

21Patents
5h-index
32Co-inventors
61Inventor score

Filing activity: Feb 15, 2013 → May 18, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9123566B2 Complementary metal-oxide-semiconductor device comprising silicon and germanium and method for manufacturing thereof Electricity 15 Active
US9476143B2 Methods using mask structures for substantially defect-free epitaxial growth Electricity 10 Active
US9842777B2 Semiconductor devices comprising multiple channels and method of making same Electricity 9 Active
US10269929B2 Internal spacer formation for nanowire semiconductor devices Performing Operations; Transporting 7 Active
US9070712B2 Methods for manufacturing a field-effect semiconductor device Electricity 7 Active
US9633891B2 Method for forming a transistor structure comprising a fin-shaped channel structure Electricity 4 Active
US10361268B2 Internal spacers for nanowire semiconductor devices Electricity 3 Active
US10090393B2 Method for forming a field effect transistor device having an electrical contact Electricity 1 Active
US11195767B2 Integration of a III-V device on a Si substrate Electricity 1 Active
US9478544B2 Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device Electricity 1 Active
US10714595B2 Method of forming a semiconductor device comprising at least one germanium nanowire Electricity 0 Active
US11387350B2 Semiconductor fin structure and method of fabricating the same Electricity 0 Active
US8828826B2 Method for manufacturing a transistor device comprising a germanium based channel layer Electricity 0 Active
US11355618B2 Low parasitic Ccb heterojunction bipolar transistor Electricity 0 Active
US10340139B2 Methods and mask structures for substantially defect-free epitaxial growth Electricity 0 Active
US9343329B2 Contact formation in Ge-containing semiconductor devices Electricity 0 Active
US9502415B2 Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device Electricity 0 Active
US9299563B2 Method for forming a strained semiconductor structure Electricity 0 Active
US11557503B2 Method for co-integration of III-V devices with group IV devices Electricity 0 Active
US11646200B2 Integration of a III-V construction on a group IV substrate Electricity 0 Active
US9972622B2 Method for manufacturing a CMOS device and associated device Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.