Backside contact for thermal displacement in a multi-wafer stacked integrated circuit
US11195818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2019 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Nov 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.